The present invention is relating to a semiconductor wafer for avoiding probed marks while testing, particularly to a semiconductor wafer with bumps and separate testing pads or bumps.
Conventionally, wafer sorting or chip probing of integrated circuits is to probe directly bonding pads or bumps on wafer with probe needles which will causes probed marks on bonding pads or bumps. These probed marks will cause reliability issues in further processing such as package/module assmbly.
A semiconductor device designed to avoid probed marks on bumps while testing is disclosed in U.S. Pat. No. 5,554,940, xe2x80x9cBumped semiconductor device and method for probing the samexe2x80x9d. There are bumps of flip chip application and separate test pads on a semiconductor chip so that no need for probing the bumps while testing. As shown in FIGS. 1, 2, 3, a semiconductor chip 10 has a plurality of bonding pads 12 embedded between inner dielectric layer 18, 20 and insulation layer 22. The bonding pads 12 are connected with the integrated circuits of semiconductor chip 10 by using the metal plug 16 and metal interconnect 14, and there are a plug 38 piercing through the insulation layer 22 on the bonding pad 12 and a conduction pad 34 above the plug 38 for linking the redistribution structure 26 on the surface having bonding pads 12. Each redistribution structure 26 has a test pad 28, a bump pad 30, a bump interconnect 32 and a test interconnect 36 (as shown in FIG. 2), electrically connecting the bump pad 30 with the corresponding bonding pad 12 or test pad 28 by the bump interconnect 32, and electrically connecting the test pad 28 with the corresponding bonding pad 12 by the test interconnect 36. As shown in FIG. 2, the plurality of redistribution structures 26 are covered by a passivation layer 40, the passivation layer 40 has a plurality of openings 42 so as to open the test pad 28 and bump pad 30 (as shown in FIGS. 3, 4), wherein the test pad 28 is used to be probed by the probe needle 50. Besides, as shown in FIGS. 2, 4, a bump 48 is formed on the bump pad 30 and a metal barrier layer 44 is formed between the bump 48 and the bump pad 30. While testing the semiconductor chip 10, test pad 28 probed by probe needle 50 conducts testing signals through test interconnect 36, conduction pad 34 and plug 38 to the bonding pad 12without testing through the bump interconnect 32. Therefore, it is impossible to know if bump interconnect 32 is in good condition or not, i.e., there is no way to tell if the bump interconnect 32 is either open or short from probing at test pad 28 which will provide incorrect test result.
The main purpose of the present invention is to provide a semiconductor wafer designed to avoid probed marks while testing. The wafer has a plurality of metal interconnects and each metal interconnect connects to the corresponding contact pad/ bump, test pad/bump and bonding pad. The contact pad/bump, being an outer connection terminal, is connected in series by the metal interconnect between the corresponding test pad/bump and bonding pad, so that the metal interconnect between the bonding pad and the contact pad can be tested during probing at the test pad/bump. Furthermore, there will be no probed marks on the contact pad/bump.
According to the present invention, a semiconductor wafer designed to avoid probed marks while testing comprises:
a plurality of semiconductor chips, each chip having an integrated circuit forming surface formed on the same plane of semiconductor wafer, wherein the chip has a plurality of bonding pads on the integrated circuit forming surface;
a plurality of cutting paths, each cutting path formed between two adjoining chips;
a plurality of metal interconnects, which are on the integrated circuit forming surface of a chip, and electrically connect with corresponding bonding pads respectively;
a passivation layer, which covers a plurality of metal interconnects, and has a plurality of the first openings and the second openings;
a plurality of test pads, which are located at the first openings of the passivation layer and each conducts to corresponding bonding pad through a corresponding metal interconnect; and
a plurality of contact pads, which are located at the second openings of the passivation layer, wherein the contact pad is connected in series by the corresponding metal interconnect between the corresponding bonding pad and test pad.